Many mobile communication devices use a radio transceiver that includes one or more digital signal processors (DSP).
For increased performance and reliability many mobile terminals presently use a type of DSP known as a baseband processor (BBP), for handling many of the signal processing functions associated with processing of the received the radio signal and preparing signals for transmission.
Many of the functions frequently performed in such processors are performed on large numbers of data samples. Therefore a type of processor known as Single Instruction Multiple Data (SIMD) processor is useful because it enables the same instruction to be performed for a whole vector of data rather than on one integer at a time. This kind of processor is able to process vector instructions, which means that a single instruction performs the same function to a limited number of data units. Data are grouped into bytes or words and packed into a vector to be operated on.
As a further development of SIMD architecture, Single Instruction stream Multiple Tasks (SIMT) architecture has been developed. Traditionally in SIMT architecture one or two vector execution units that use SIMD data-paths have been provided in association with an integer execution unit, which may be part of a core processor.
International Patent Application WO 2007/018467 discloses a DSP according to the SIMT architecture, having a processor core including an integer execution unit and a program memory, and two vector execution units which are connected to, but not integrated in the core. The vector execution units may be Complex Arithmetic Logic Units (CALU) or Complex Multiply-Accumulate Units (CMAC). The data to be processed in the vector execution units are provided from data memory units connected to the vector execution units through an on-chip network.
The memory units comprise address generation units which are arranged to control the read or write order at any given time. For increased flexibility, the address generation unit can enable different readout modes, or patterns, such as reading from every nth address in the memory. These modes have to provide a regular pattern, which limits the possible ways data can be read or written. Further, the available modes are preselected for a particular address generation unit, and cannot be changed.
The article Nilsson, A and Tell, E: “An 11 mm2, 70 mW fully programmable baseband processor for mobile WiMAX and DVB-T/H in 0.12 μm CMOS”, describes a SIMT type DSP and briefly states that “as the memory banks can accept external addressing from the network, integer memories as well as accelerators can be used to provide address sequences for irregular vector addressing. This also provides the ability to do indirect vector addressing”. This article does not address any of the problems involved in actually implementing such a solution, and also hence does not provide a workable solution.